Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

ABSTRACT

This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

FIELD OF THE INVENTION

This invention generally relates to complementary metal oxidesemiconductor (CMOS) circuits comprising field effect transistors (FETs)fabricated with one or more ion implantation steps. More particularly,it relates to the ways in which these ion implantation steps may becombined with in situ or ex situ heat treatments to avoid and/orminimize implant-induced amorphization (a potential problem forsource/drain regions in FETs in ultrathin silicon on insulator layers)and implant-induced plastic relaxation of strained source/drain regions(a potential problem for strained channel FETs in which the channelstrain is provided by embedded source/drain regions lattice mismatchedwith an underlying substrate layer).

BACKGROUND OF THE INVENTION

Historically, most performance improvements in semiconductorfield-effect transistors (FET) have been achieved by scaling down therelative dimensions of the device. This trend is becoming increasinglymore difficult to maintain as the devices reach their physical scalinglimits. As a consequence, advanced FETs and the complementary metaloxide semiconductor (CMOS) circuits in which they can be found areincreasingly relying on strain engineering and specialtysilicon-on-insulator substrates to achieve desired circuit performance.However, the ion implantation steps used in fabricating the FETs relyingon these enhancements present two particular challenges.

The first challenge pertains to source/drain (S/D) implants in CMOSfabricated in ultrathin silicon-on-insulator (UTSOI) substrates, wherethe UTSOI layer is typically in the range from 6 to 30 nm in thickness.It is difficult to implant the desired concentration of certain dopantspecies in the S/D regions without amorphizing the entire SOI layer. Ifthere is no crystalline Si left under the amorphized S/D regions to actas a seed or template, the S/D recrystallization will be highlydefective (and thus unsuitable for high performance devices).Through-SOI-thickness amorphization is of particular concern with heavyions such as As⁺ and with UTSOI layers on the thin end of the thicknessrange. This problem is illustrated in FIG. 1, in which the basic stepsof a S/D implant and annealing process for an UTSOI FET having a desiredoutcome are shown in FIGS. 1A-1C and the basic steps of a S/D implantand annealing process having an undesired outcome are shown in FIGS.1D-1F.

FIG. 1A shows UTSOI FET 10 at an early stage of processing. UTSOI FET 10comprises single crystal UTSOI layer 20 disposed on buried oxide (box)layer 30 on base substrate 40, with conductive gate 50 disposed on gatedielectric 60 over UTSOI channel region 70 separating UTSOI S/D regions80. FIG. 1B shows the structure of FIG. 1A after S/D regions 80 havebeen amorphized with ion implant 90 to create amorphized S/D regions100. Residual crystalline regions 80′ remain under amorphized S/Dregions, providing a template for the amorphized S/D regions torecrystallize by solid phase epitaxy (SPE) during subsequent activationannealing to produce single-crystal S/D regions 80″, as shown in FIG.1C.

FIGS. 1D-1F show what happens when the same implant 90 is applied to theslightly thinner UTSOI layer 120 of FIG. 1D. In this case, ion implant90 produces amorphized S/D regions 130 extending all the way to boxlayer 30, as shown in FIG. 1E. Due to the lack of a single crystal Sitemplate, recrystallization of these amorphized S/D regions duringsubsequent activation annealing thus produces polycrystalline S/Dregions 140, as shown in FIG. 1F. This is undesirable because dopedpolycrystalline Si has a much higher resistance than crystalline Sihaving the same dopant density.

The second challenge pertains to FETs relying on strain engineering. Inthese FETs, the channel regions of the transistors are strained toproduce an increase in the mobility of the charge carriers and thus anincrease in the on-state current of the device (at a given drainpotential). One method that is currently used to induce channel strainis to grow a compressively strained SiGe layer in a recessed regionadjacent to the channel region of the device, as described in U.S. Pat.No. 6,621,131, “Semiconductor Transistor Having a Stressed Channel,”issued Sep. 16, 2003. The SiGe layer then serves as the S/D of thedevice and imparts uniaxial strain on the channel. The amount of strainin the channel will be proportional to the stress applied by the SiGelayer, which would typically increase with the Ge content of the SiGe.Since increased strain in the channel correlates with better deviceperformance, there is a great interest in SiGe stressors having a highGe content.

One of the primary challenges in using single-crystal strained regionsas a stressor for the channel is to prevent the formation of strainrelieving dislocations during strained region growth and subsequentprocessing. It has been found that the ion implantation step that isused to dope and electrically activate the S/D regions facilitates therelaxation of the strain in the SiGe S/D regions, as illustrated inFIGS. 2A-2F, which show, in cross section view, the steps in fabricatinga FET with channel strain induced by embedded SiGe S/D regions whoseprocessing requires at least one ion implantation step.

FIG. 2A shows SOI FET 200 at an early stage of processing. SOI FET 200comprises single crystal SOI layer 210 disposed on buried oxide (box)layer 220 on base substrate 230, with conductive gate 240 disposed ongate dielectric 250 over SOI channel region 260 separating SOI S/Dregions 270. FIG. 2B shows the structure of FIG. 2A after S/D regions270 have been etched away to form cavities 280. Cavities 280 are thenreplaced by epitaxially grown SiGe stressor S/D regions 290 which exerta force on the channel region, as indicated by arrows 300 in FIG. 2C.Implantation of SiGe regions 290 by non-amorphizing implant 310 producesmultiple defects 320 as shown in FIG. 2D. These defects act asnucleation sites for strain-relieving dislocations 330 that form duringsubsequent activation annealing, as shown in FIG. 2E, where short arrows340 indicate the reduced force of the S/D regions on channel region 260as compared to longer arrows 300 in FIG. 2C.

Certain implantation conditions (particularly those involving heavy ionssuch as As⁺) can result in a significant and irreversible reduction instrain after a prescribed thermal treatment step called an “activationanneal.” Since the driving force for strain relaxation increases withstrain, SiGe alloys with a high Ge content are particularly susceptibleto undesired relaxation. A method for S/D ion implantation andactivation that minimizes S/D plastic relaxation and preserves as muchstrain as possible would be highly desirable.

The efficacy of heated implants in reducing ion implant damage in bulksemiconductors has been known for some time. The threshold dose ofimplanted ions required to amorphize a given semiconductor region in asubstrate increases with substrate temperature because the transmitionfrom a crystalline material to an amorphous one is determined by thecompetition between the temperature-independent rate at which the damageand disorder are generated by the implanted ions and thetemperature-dependent rate at which the implant damage can bespontaneously repaired. For example, the threshold dose required foramorphization with 200 keV B implanted at low current densities into100-oriented single crystal Si increases by a factor of 40 as the Sisubstrate temperature is increased from 200 K to 300 K as described byF. F. Morehead et al., J. Appl. Phys. 43 1112 (1972). While these andsimilar effects are well known for bulk Si and the III-Vs, the benefitsof hot implants have not been previously applied to solve the newproblems addressed by the present invention, namely, reduction and/orelimination of (i) implant-induced source/drain amorphization in UTSOICMOS, and (ii) implant-induced plastic relaxation in FETs with strainedsource/drain regions.

It is therefore an object of this invention to provide an ionimplantation method that allows the desired dopant density profiles tobe achieved with satisfactorily limited amorphized layer thicknessesand/or satisfactorily low levels of strain relaxation.

It is a further object of this invention to provide an alternative tothe ion implantation method above, wherein said alternative alsoproduces satisfactorily limited amorphized layer thicknesses and/orsatisfactorily low levels of strain relief, that is easier to implementwith existing tooling.

SUMMARY OF THE INVENTION

The present invention teaches the use of ion implantation in combinationwith in situ or ex situ heat treatments as a method for avoiding orreducing ion implant-induced amorphization and ion implant-inducedplastic relaxation.

In a first embodiment of the invention, ion implantation is combinedwith in situ heat treatment, i.e., implants having the potential toproduce undesired amorphization or strain relief are performed atelevated temperature with respect to room temperature. In particular,the invention describes:

-   -   the fabrication of an FET device in a bulk semiconductor or        semiconductor-on-insulator layer in which at least some ion        implantation of said FET's source/drain regions is performed        while the semiconductor layer is held at an elevated        temperature;    -   the fabrication of an FET device in a bulk semiconductor or        semiconductor-on-insulator layer in which at least some features        in addition to the FET's source/drain regions are implanted        while the semiconductor layer is held at an elevated        temperature; and    -   the fabrication of an FET device in a bulk semiconductor or        semiconductor-on-insulator layer, the FET device comprising        strained source/drain regions, in which at least some        implantation of the strained source/drain regions is performed        while the semiconductor layer is held at an elevated        temperature.

The elevated temperatures for the in situ heat treatments of thisinvention would typically be in the range from 70 to 900° C., preferablybe in the range from 150 to 550° C., and most preferably be in the rangefrom 200 to 350° C. Ion implantation at elevated temperatures may alsobe conveniently described as “hot implantation,” “hot implants,” “heatedimplantation,” or “heated implants.”

In a second embodiment of the invention, ion implantation is combinedwith ex situ heat treatments in a “divided-dose-anneal-in-between”(DDAB) scheme that avoids the need for tooling capable of performing hotimplants. In this embodiment, the desired total dose is divided intosmaller sub-doses, each of which is below the threshold for amorphizingthe entire thickness of the S/D regions (for the case of UTSOI) orgenerating significant strain relief (for the case of strained S/Dregions). Annealing performed after each implant recrystallizes theamorphized regions by solid phase epitaxy and/or reduces damageaccumulation to a negligible level.

Another aspect of the invention provides FETs and CMOS circuitsfabricated with heated implants and/or the DDAB method of implantation.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, objects, and advantages of the presentinvention will become apparent upon a consideration of the followingdetailed description of the invention when read in conjunction with thedrawings, in which:

FIGS. 1A-1E show, in cross section view, the basic steps of a S/Dimplant and annealing process for a UTSOI FET having a desired outcome(FIGS. 1A-1C) and the basic steps of a S/D implant and annealing processhaving an undesired outcome (FIGS. 1D-1F);

FIGS. 2A-2E show, in cross section view, the steps in fabricating a FETwith channel strain induced by embedded SiGe S/D regions whoseprocessing requires at least one ion implantation step;

FIGS. 3A-3E show, in cross section view, some structures which may beheated during ion implantation according to the method this invention;

FIGS. 4A-4G show, in cross section view, the steps of a DDAB methodapplied to the fabrication of a UTSOI FET in a CMOS circuit;

FIGS. 5A-5H show, in cross section view, the steps of a DDAB methodapplied to the fabrication of a strain-engineered FET in a CMOS circuit,where the strain-engineered FET has channel strain induced by embeddedS/D regions;

FIG. 6 compares reflectance vs. wavelength data for SOI layers implantedwith As⁺ at three different temperatures to data for a control samplethat did not receive an implant;

FIG. 7 illustrates the utility of hot implants with a comparison of highresolution x-ray diffraction (HRXRD) rocking curve (RC) data for anas-grown SiGe sample (curve A) to SiGe samples implanted with As⁺ at3000° C. (curve B) or room temperature (curve C);

FIG. 8 shows HRXRD RC data for the samples of FIG. 7 after an anneal at1080° C. for 1 s (using a 150° C./s heating ramp rate); and

FIG. 9 illustrates the strain-preserving features of the DDAB techniquewith a comparison of HRXRD RC data for the as-grown SiGe sample of FIG.7A (curve A) to identical SiGe samples given a single As⁺ implant andanneal (curve B) or a two-step DDAB implant and anneal (curve C).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, FIGS. 3A-3E show, in cross section view,some structures which may be heated during ion implantation according tothe method of this invention. FIG. 3A shows ion implant 370 beingapplied to partially completed FET 380 in bulk semiconductor 390, wherepartially completed FET 380 comprises conductive gate 400 on gatedielectric 410 over channel region 420 separating S/D regions 430. FIG.3B shows ion implant 370 being applied to partially completed FET 450 insemiconductor-on-insulator layer 460 on box layer 470 on base substrate480, where partially completed FET 450 comprises conductive gate 490 ongate dielectric 500 over channel region 510 separating S/D regions 520.The conditions of ion implant 370 would typically be selected so that atleast some of S/D regions 430 and 520 would be implanted while gates 400and 490 would protect channel regions 420 and 510 from being implanted.

FIG. 3C shows ion implant 550 being applied tosemiconductor-on-insulator substrate 560 comprisingsemiconductor-on-insulator layer 570 on box layer 580 on base substrate590. In this case, the conditions of ion implant 550 might be selectedto provide a peak concentration of implanted species in base substrate590 under box layer 580 rather than in semiconductor-on-insulator layer570 on top of box layer 580. Such implant conditions may be useful forfabricating certain back-gated devices in which the semiconductordirectly under the box functions as a back gate. FIG. 3C thus providesan example of how heated implants in the range from 70° C. to 900° C.may be used in fabricating FET devices in a bulk semiconductor orsemiconductor-on-insulator layer so that at least some features inaddition to the FET's source/drain regions are implanted, since withheated implants it becomes possible to implant a high concentration ofdopants into base substrate 590 without running the risk of amorphizingsemiconductor-on-insulator 570.

FIG. 3D shows ion implant 600 being applied to partially completed FET610 in bulk semiconductor 620, where partially completed FET 610comprises conductive gate 630 on gate dielectric 640 over channel region650 separating semiconductor S/D regions 660. Semiconductor S/D regions660 are strained and formed from a different material than channelregion 650. The conditions of ion implant 600 might be selected toprovide a light doping of S/D regions 660, but no amorphization. Forexample, channel region 650 might comprise Si and S/D regions 660 mightcomprise strained SiGe. The force of S/D regions 660 on channel region650 is indicated by arrows 670. FIG. 3E shows thesemiconductor-on-insulator analog of FIG. 3D. Ion implant 600 is nowbeing applied to partially completed FET 700 insemiconductor-on-insulator layer 710 on box layer 720 on base substrate730, where partially completed FET 700 comprises conductive gate 740 ongate dielectric 750 over semiconductor-on-insulator channel region 760separating strained semiconductor S/D regions 770, where arrows 780indicate the stress exerted on channel region 760 by S/D regions 770.

Patterned masking layers may be used in these hot implant processes.Ideally, patterned masking layers not remaining in the final device(i.e., disposable masking layers) would be formed prior to the hotimplantation step and removed after the hot implantation step. Thesepatterned masking layers would typically define first source/drain (orother) regions that would be subjected to the hot implantation andsecond source/drain (or other) regions that would be protected from thehot implantation. These disposable masking layers are preferably easilypatterned, thermally stable, and easy to remove without damaging theunderlying substrate. An example of a mask material meeting theserequirements is amorphous carbon with a hydrogen content less than about15 atomic %. This material is thermally stable and may be patterned (aswell as removed) by oxygen-based plasma etching without damage tounderlying oxide, nitride, and/or silicon substrate layers. While oxideand nitride layers are also thermally stable and perhaps more easilypatterned than amorphous carbon, such materials are harder to removeselectively with respect to the substrate. Multilayer masks comprisingone or more upper oxide and/or nitride layers on a base layer ofamorphous carbon may provide the optimum compromise between ease ofpatterning and selective removal.

In a second embodiment of the invention, ion implantation is combinedwith ex situ heat treatments in a “divided-dose-anneal-in-between”(DDAB) scheme. In this embodiment, the desired total dose is dividedinto smaller sub-doses, each of which is below the threshold foramorphizing the entire thickness of the S/D regions (for the case ofUTSOI) or generating significant strain relief (for the case of strainedS/D regions). Annealing performed after each implant restores the S/Dregions to their pre-implant levels of crystallinity and/or strainbefore the accumulated damage reaches a level that is irreversible.Depending on the implantation conditions (species, energy, dose, ionangle of incidence, substrate temperature, etc.), some to none of thethickness of the implanted S/D regions may be amorphized. For high-doseimplants producing an amorphous layer, the between-implant annealsrestore the initial crystallinity by solid phase epitaxy; for low-dose,non-amorphizing implants, the between-implant anneals remove theincipient nucleation sites for strain-relieving dislocations before theyfully develop.

The basic DDAB method of ion implantation comprises

-   -   selecting a substrate including a semiconductor layer;    -   defining first semiconductor layer regions that will be        subjected to at least two subsequent ion implantation steps and        second semiconductor layer regions that will be protected from        said at least two subsequent ion implantation steps;    -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a first ion implantation;    -   subjecting the substrate to a first anneal;    -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a final ion implantation;        and subjecting the substrate to a final anneal;        wherein residual damage left in the first semiconductor layer        regions (as measured by strain loss and/or defect density) after        the final anneal is less than the residual damage that would be        left in the first semiconductor layer regions if the above        process steps were performed without the first anneal.

The DDAB method would typically further include

-   -   applying a masking layer defining the first and second        semiconductor layer regions in the substrate before each implant        step and removing the masking layer from the substrate before        each annealing step; or    -   applying a masking layer defining the first and second        semiconductor layer regions in the substrate before the first        implant step and not removing the masking layer from the        substrate until after the final implant step.

The DDAB method may contain any number of implant and anneal steps toachieve the desired dopant dose and profile with sufficiently low damageto the semiconductor layer regions being implanted. For more than twoimplant steps, the basic DDAB method above would further include one ormore cycles of supplemental implant and annealing steps comprising

-   -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a supplemental ion        implantation; and    -   subjecting the substrate to a supplemental anneal;        the cycles performed after the first anneal and before the final        implant, wherein residual damage left in the first semiconductor        layer regions (as measured by strain loss and/or defect density)        after the final anneal is less than the residual damage that        would be left in the first semiconductor layer regions if the        above process steps were performed without the first and the        supplemental annealing steps.

The DDAB method of ion implantation may also be implemented withoutregard to the final levels of semiconductor layer damage, in accord withthe previously described steps of

-   -   selecting a substrate including a semiconductor layer;    -   defining first semiconductor layer regions that will be        subjected to at least two subsequent ion implantation steps and        second semiconductor layer regions that will be protected from        said at least two subsequent ion implantation steps;    -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a first ion implantation;    -   subjecting the substrate to a first anneal;    -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a final ion implantation;        and    -   subjecting the substrate to a final anneal; in combination with        the step of    -   applying a masking layer defining the first and second        semiconductor layer regions in the substrate before the first        implant step, the masking layer remaining in place until after        the final implant step.

This version of the DDAB method may also include one or more cycles ofsupplemental implant and annealing steps comprising

-   -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a supplemental ion        implantation; and    -   subjecting the substrate to a supplemental anneal;        the cycles performed after the first anneal and before the final        implant.

Suitable materials for masks used with DDAB are similar to thosedescribed above for hot implants. In addition, between-implant annealtemperatures of 230° C. and below are expected to be compatible withmany patterned photoresist layers. If higher temperatures are needed (asexpected), one may strip the resist before each annealing step andreapply it before each implant step.

FIG. 4 shows the steps of a DDAB method applied to the fabrication of aUTSOI FET in a CMOS circuit. FIG. 4A shows partially completed FETs 800and 810 in UTSOI layer 820 disposed on box layer 830 disposed on basesubstrate 840. One of partially completed FETs 800 and 810 might be ann-channel FET (nFET) and the other of FETs 800 and 810 might be ap-channel FET (pFET). FETs 800 and 810 comprise gates 850 and 852 andgate dielectrics 860 and 862 disposed on channel regions 880 and 882separating S/D regions 870 and 872. FETs 800 and 810 are separated byshallow trench isolation regions 890. FIG. 4B shows the structure ofFIG. 4A after application of patterned masking layer 900 to protect FET810 from one or more subsequent ion implants. FIG. 4C shows thestructure of FIG. 4B being subjected to a first ion implant 910 whichamorphizes an upper portion of S/D regions 870 of FET 800 to formamorphized S/D regions 920 which do not extend all the way down to boxlayer 830. The structure of FIG. 4C is then annealed, allowingamorphized S/D regions 920 to recrystallize by solid phase epitaxy toform recrystallized S/D regions 930, as shown in FIG. 4D. Patternedmasking layer 900 may remain in place during the anneal, or be removedbefore the anneal and replaced after the anneal. FIG. 4E shows thestructure of FIG. 4D being subjected to a final ion implant 940 whichmay be the same as or different from first ion implant 910. Typicallyion implant 940 would be the same as or very similar to ion implant 910,with the sum of the doses of implants 910 and 940 equal to the totaldesired implant dose. Ion implant 940 again amorphizes an upper portionof S/D regions 870 of FET 800 to form amorphized S/D regions 920′ whichdo not extend all the way down to box layer 830. The structure of FIG.4E is then annealed, allowing amorphized S/D regions 920′ torecrystallize by solid phase epitaxy to form recrystallized S/D regions930′. Activation annealing may be included in the recrystallizationanneal, or performed separately. Patterned masking layer 900 is removedbefore or after these last annealing steps to produce the structure ofFIG. 4G.

FIG. 5 shows the steps of a DDAB method applied to the fabrication of astrain-engineered FET in a CMOS circuit, where the strain-engineered FEThas channel strain induced by embedded S/D regions. FIG. 5A showspartially completed FETs 1000 and 1010 in semiconductor layer 1020disposed on box layer 1030 disposed on base substrate 1040. One ofpartially completed FETs 1000 and 1010 might be an nFET and the other ofFETs 1000 and 1010 might be a pFET. FETs 1000 and 1010 comprise gates1050 and 1052 and gate dielectrics 1060 and 1062 disposed on channelregions 1080 and 1082 separating S/D regions 1070 and 1072. FETs 1000and 1010 are separated by shallow trench isolation regions 1090. FIG. 5Bshows the structure of FIG. 5A after S/D regions 1020 of FET 1000 havebeen replaced by embedded S/D regions 1100, according to prior artmethods illustrated in FIGS. 2A-2C. Embedded S/D regions 1100 arestrained and exert a stress on channel region 1080. FIG. 5C shows thestructure of FIG. 5B after application of patterned masking layer 1110to protect FET 1010 from one or more subsequent ion implants. FIG. 5Dshows the structure of FIG. 5C being subjected to a non-amorphizingfirst ion implant 1120 to produce lightly damaged S/D regions 1130including many small defects indicated by circles 1140. It is believedthat defects 1140 represent damage regions that are too small orotherwise insufficient to nucleate stacking faults or otherstrain-relieving dislocations. The structure of FIG. 5D is then annealedto produce repaired S/D regions 1150, as shown in FIG. 5E. Patternedmasking layer 1110 may remain in place during the anneal, or be removedbefore the anneal and replaced after the anneal. FIG. 5F shows thestructure of FIG. 5E being subjected to a non-amorphizing final ionimplant 1160 which may be the same as or different from first ionimplant 1120. Typically ion implant 1160 would be the same as or verysimilar to ion implant 1120, with the sum of the doses of implants 1120and 1160 equal to the total desired implant dose. Ion implant 1160 againproduces lightly damaged S/D regions 1130′ including many small defectsindicated by circles 1140′. The structure of FIG. 5F is then annealed toproduce repaired S/D regions 1150 which still has all or most of theirinitial strain, as shown in FIG. 5G. Activation annealing may beincluded in the recrystallization anneal, or performed separately.Patterned masking layer 1110 is removed before or after these lastannealing steps to produce the structure of FIG. 5H.

Another aspect of the invention provides at least one FET device in asemiconductor layer, the FET device comprising source/drain regionssubjected to ion implantation while the semiconductor-on-insulator isheld at an elevated temperature in the range from 70° C. to 900° C.While the temperature is held at an elevated temperature the temperaturetakes into account the temperature rise of thesemiconductor-on-insulator due to self heating during ion implantation,which typically is in the range from 0° C. to 50° C. Typically,temperature increases encountered without deliberate wafer cooling areless than 25° C., but may be as high as 50° C. for high does, highcurrent implants.

This invention also provides an FET device in a semiconductor layer, theFET device comprising source/drain regions is subjected to adivided-dose-anneal-in-between (DDAB) method of ion implantationcomprising the steps of

-   -   selecting a substrate including a semiconductor layer;    -   defining first semiconductor layer regions that will be        subjected to at least two subsequent ion implantation steps and        second semiconductor layer regions that will be protected from        said at least two subsequent ion implantation steps;    -   protecting the second semiconductor layer regions from exposure        to ion implantation;    -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a first ion implantation;    -   subjecting the substrate to a first anneal;    -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a final ion implantation;        and    -   subjecting the substrate to a final anneal;        wherein residual damage left in the first semiconductor layer        regions (as measured by strain loss and/or defect density) after        the final anneal is less than the residual damage that would be        left in the first semiconductor layer regions if the above        process steps were performed without the first anneal.

This invention also provides FET devices subjected to DDAB methods ofion implantation with multiple implant and annealing cycles, such as,for example, multiple implant and annealing cycles comprising the abovefirst and final implants and anneals plus one or more cycles ofsupplemental implant and annealing steps comprising

-   -   subjecting the first semiconductor layer regions (but not the        second semiconductor layer regions) to a supplemental ion        implantation; and    -   subjecting the substrate to a supplemental anneal;        the cycles performed after the first anneal and before the final        implant, wherein residual damage left in the first semiconductor        layer regions (as measured by strain loss and/or defect density)        after the final anneal is less than the residual damage that        would be left in the first semiconductor layer regions if the        above process steps were performed without the first and the        supplemental annealing steps.

The FETs of this invention may be combined with other FETs to formcomplementary metal-oxide-semiconductor (CMOS) or other circuits.

The semiconductor layers described in this invention may comprise bulksemiconductors; semiconductor-on-insulator layers; or a combination ofbulk and semiconductor-on-insulator layers such that at least part ofthe semiconductor layer is bulk and at least part of the semiconductorlayer is disposed on an insulator; the semiconductor layers comprisingone or more of Si, SiC, Ge, GeC, SiGe and SiGeC; these materials inlayered combinations; these materials strained, partially strained (orpartially relaxed) and/or unstrained (or fully relaxed).

The semiconductor layer may comprise, for example, asilicon-on-insulator layer with a thickness less than 30 nm and/or FETscomprising semiconductor S/D regions separated by a semiconductingchannel region, wherein said S/D regions and said channel regionscomprise different semiconductor materials, and wherein said S/D regionsare strained, partially strained, or unstrained. Particularly favoredexamples of the FETs to which the hot implant and DDAB methods of thisinvention may be applied include (i) FETs comprising a semiconductingchannel region of Si and S/D regions of a strained SiGe alloy having aGe content equal to or greater than 25 atomic percent, and (ii) FETscomprising a semiconducting channel region of Si and S/D regions of astrained SiC alloy having a C content greater than 0.5 atomic percent.The semiconductor layers may comprise of a single crystal orientationsuch as (100) or two or more single crystal orientations (as typified byhybrid orientation substrate technology) such as regions of (100) and(110).

The elevated temperatures for the heated implants of this inventionwould typically be in the range from 70 to 900° C., preferably be in therange from 150 to 550° C., and most preferably be in the range from200-350° C. Annealing for the DDAB method would typically include anyannealing process known to the art, including furnace annealing, rapidthermal annealing, and laser annealing, for time and temperature rangesknown to the art, e.g., temperatures in the range from 150 to 1350° C.and times in the range from 24 hours to sub-milliseconds. Gas ambientsmay be selected from those known to the art, typically N₂ or Ar with orwithout additional additives selected from the group NH₃, H₂O, H₂, O₂,NO, N₂O, etc.

The ion implantation of this invention may be performed with any ionknown to the art, including atomic ions, molecular ions, singly-chargedions, and multiply-charged ions. Particularly favored ions include theions of As, B, B₁, BF₂, Ge, P and Sb. The conditions for the individualimplants comprising the DDAB method may be the same or different in oneor more particulars (for example, first and final implants might utilizethe same species and energy but be different in angle of incidence).

Three examples of the invention will now be described. In the first, itis shown that in situ heating during ion implantation can prevent theamorphization of SOI layers that would occur if the same implants wereperformed at room temperature such as in the range from 20° C. to 25° C.In the second example, we show how the dependence of amorphization depthon As implant dose may be used to calculate an optimum implementation ofthe DDAB technique in a semiconductor-on-insulator layer. In the thirdexample, we show how the hot implant and DDAB techniques may be used topreserve the strain in pseudomorphic SiGe layers grown on Si.

EXAMPLE 1

The example shows that in situ heating during ion implantation canprevent the amorphization of SOI layers that would occur if the sameimplants were performed at room temperature. SOI layers 28 nm inthickness were implanted at 26, 150, or 300° C. with 3×10¹⁵/cm² 50 keVAs⁺, an implant that has an average projected range (Rp) of about 340 Åand would ordinarily completely amorphize the SOI layer. The reflectancevs. wavelength data of FIG. 6 indicates that the SOI layer has indeedbeen amorphized in the 26 and 150° C. samples (curves B and C,respectively), but remains crystalline (with a reflectance curve nearlyidentical to curve A of the unimplanted control sample) for the 300° C.implant (curve D). The sheet resistance (Rs) measurements of Table Icorroborate these results: after annealing in N₂ at 900° C. for 1 min,the 26 and 150° C. samples have Rs in the range of 8-11 kohm/square,consistent with a recrystallization of the amorphous SOI layer topolycrystalline Si; in contrast, the 300° C. sample has a Rs of 790ohm/sq, consistent with doped single-crystal Si. In addition, theimplanted As⁺ is quite substantially activated even as-implanted (Rs˜15.5 kohm/sq) and is more activated (with an Rs of 4.4 kohm/sq) aftervery mild annealing (500° C./1 min) than the 26 and 150° C. samples areafter 900° C./min.

Table I shows Rs measurements (ohm/sq) of samples implanted with3×10¹⁵/cm² 50 keV As⁺. TABLE I Anneal/Implant Temperature 26° C. 150° C.300° C. as-implanted >1000 k >1000 k 15.5 k 500° C./1 min >1000 k >1000k 4.4 k 900° C./1 min 10.7 k 8.2 k 790

EXAMPLE 2

In the second example; we show how one may use the dependence ofamorphization depth on implant dose to calculate an optimumimplementation of the DDAB technique in a semiconductor-on-insulatorlayer disposed on a buried oxide (box). SOI layers 160 nm in thicknesswere implanted at room temperature with 100 keV As⁺ (Rp about 71 nm) atdoses of 1.25, 2.5, and 5.0×10¹⁵/cm² to produce surface amorphous layershaving thicknesses of 91, 111, and 117 nm respectively. None of thesedoses were sufficient to amorphize the entire 160 nm thickness of theSOI layer. However, SOI layers thinner than about 110 nm in thicknesswould be expected to totally amorphize at doses higher than2.5×10¹⁵/cm², form polycrystalline Si upon activation annealing.Dividing the 2.5×10¹⁵/cm² dose into two doses of 1.25×10¹⁵/cm² wouldleave a residual crystalline layer between the 91 nm amorphization depthand the top of the box after each implant. Annealing between theimplants allows the crystallinity of the sample to be restored (by SPEtemplating from the residual crystalline layer) before the next implantand results in a crystalline material after a final activation anneal.

EXAMPLE 3

In the third example, we show how the hot implant and DDAB techniquesmay be used to preserve the strain in pseudomorphic SiGe layers grown onSi. FIGS. 7-9 show high resolution x-ray diffraction (HRXR-D) (004)rocking curves (RCs) of a structure comprised by 40-nm-thickSi_(0.70)Ge_(03.0) layers epitaxially grown on (100) Si substrate, takenbefore and after implantation with As⁺ to a dose below the amorphizationthreshold dose. In FIGS. 7-9, the ordinate represents the intensity ofdiffracted x-ray in counts/second and the abscissa represents deltarocking angle omega in unity of seconds of degree, having the scaleorigin set at the Si substrate diffraction peak. The SiGe peak (atnegative angles in FIGS. 7-9) typically comprises a main peak borderedby weaker satellite peaks (thickness fringes or Pendellosungoscillations) whose spacing allows a precise estimate of the SiGethickness. The intensities of the main peak and the satellite peaks arehighest when the SiGe is perfectly ordered and defect-free, and decreasewith increasing film disorder. The angular separation of the SiGediffraction peak from that of Si substrate correlates with the magnitudeof the compressive strain in the epi-layer.

FIG. 7 demonstrates the utility of hot implants by comparing the RCs ofan as-grown sample (curve A) to samples implanted with 2×10¹³/cm², 50keV As⁺ at 0° tilt at 300° C. (curve B) or room temperature (curve C).The as-grown sample has a strain of 1.17% and very distinct thicknessfringes; the hot implanted sample has nearly identical thickness fringes(indicating negligible implant damage) and very slightly increasedstrain (1.20%). In contrast, the sample implanted at room temperatureshows no main peak and thickness fringes in the noise, a clearindication of severe damage.

FIG. 8 shows the RCs of samples of FIG. 7 after an anneal at 1080° C.for 1 s (using a 5150° C./s heating ramp rate). RC (curve A) for theunimplanted sample shows a strain of 1.14%, indicating that the initialstrain is not significantly decreased by annealing alone. RC (curve B)for the hot implanted sample shows a strain of 1.09%, again very closeto the pre-implant, pre-anneal value. RC (curve C) for the sampleimplanted at room temperature shows a restoration of the SiGe peak(indicative of substantial damage repair), but much reduced strain 110(0.65%). FIGS. 7 and 8 thus demonstrate that implant temperature is thekey factor in determining whether a given implant energy/dose andsubsequent activation anneal will preserve the initial strain or verysubstantially reduce it.

FIG. 9 illustrates the strain-preserving features of the DDAB technique.RC (curve A) shows the as-grown sample of FIG. 7A, which had an initialstrain of 1.17%. RC (curve B) shows a sample subjected to asingle-step-implant/anneal sequence comprising a room temperatureimplant of 2×10¹³/cm², 50 keV As⁺ followed by an anneal at 650° C. for110 min, resulting in a final strain of 0.88% (a significant loss). RC(curve C) shows the contrasting results of the DDAB technique using adouble-step-implant/anneal sequence in which the 2×10¹³/cm² As⁺ dose isevenly divided into two doses of 1×10¹³/cm², with each implant followedby an anneal at 650° C. for 110 min. The strain in this case is 1.12%,very close to the original value of 1.17%, very clearly indicating thebenefits of the DDAB technique.

It should be noted that the DDAB technique of course involves a tradeoffbetween the process time for the additional implant and annealing stepsand the benefits of further subdivision in implant dose (as measured bya decrease in strain loss). In many cases, thedouble-step-implant/anneal sequence may be selected optimal. However,the optimal number of subdivisions is likely to be higher for the caseof SiGe with a high Ge content and/or materials requiring high implantdoses.

While several embodiments of the invention, together with modificationsthereof, have been described in detail herein and illustrated in theaccompanying drawings, it will be evident that various furthermodifications are possible without departing from the scope of theinvention. For example, (i) multiple hot implants differing in dose,species, and/or energy might be performed with the same masking layer,and/or (ii) the individual implants comprising the DDAB method mightinclude some in situ heating during implantation. Nothing in the abovespecification is intended to limit the invention more narrowly than theappended claims. The examples given are intended only to be illustrativerather than exclusive.

1. A method for fabricating an FET device in a semiconductor layer comprising heating said semiconductor layer to an elevated temperature, and ion implanting at said elevated temperature said FET's source/drain (S/D) regions.
 2. The method of claim 1 further comprising: forming a patterned masking layer before said ion implantation, said patterned masking layer defining first source/drain regions that will be subjected to said ion implantation and second substrate regions that will protected from said ion implantation and removing said patterned mask after said ion implantation.
 3. The method of claim 1 wherein said semiconductor layer comprises a bulk semiconductor; a semiconductor-on-insulator layer; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; said semiconductor layer comprising one or more of Si, SiC, Ge, GeC, SiGe, or SiGeC; these materials in layered combinations; these materials strained, partially strained, or unstrained.
 4. The method of claim 1 wherein said semiconductor layer comprises a silicon-on-insulator layer with a thickness less than 30 nm.
 5. The method of claim 1 wherein said FET comprises semiconductor S/D regions separated by a semiconducting channel region, said S/D regions and said channel regions comprising different semiconductor materials, said S/D regions being strained, partially strained, or unstrained.
 6. The method of claim 5 wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent.
 7. The method of claim 5 wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiC alloy having a C content equal to or greater than 0.5 atomic percent.
 8. The elevated temperature of claim 1 comprising a temperature in the range from 70° C. to 900° C.
 9. The ion implantation of claim 1 wherein the ion implanted species comprises one or more of As, B, B₁, BF₂, Ge, P, and Sb.
 10. A divided-dose-anneal-in-between (DDAB) method of ion implantation comprising selecting a substrate including a semiconductor layer; defining first semiconductor layer regions that will be subjected to at least two subsequent ion implantation steps and second semiconductor layer regions that will be protected from said at least two subsequent ion implantation steps; subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a first ion implantation; subjecting said substrate to a first anneal; subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a final ion implantation; and subjecting said substrate to a final anneal; wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first anneal.
 11. The method of claim 10 further including one or more cycles of supplemental implant and annealing steps comprising subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a supplemental ion implantation; and subjecting said substrate to a supplemental anneal; said cycles performed after the first anneal and before the final implant, wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first and said supplemental annealing steps.
 12. The method of claim 10 wherein a masking layer defining said first and second semiconductor layer regions is applied to the substrate before each implant step and removed from the substrate before each annealing step.
 13. The method of claim 10 wherein a masking layer defining said first and second semiconductor layer regions is applied to the substrate before the first implant step and not removed from the substrate until after the final implant step.
 14. The method of claim 10 wherein said semiconductor layer comprises a bulk semiconductor; a semiconductor-on-insulator layer; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; said semiconductor layer comprising one or more of Si, SiC, Ge, GeC, SiGe, and SiGeC; these materials in layered combinations; these materials strained, partially strained, or unstrained.
 15. The method of claim 10 wherein said semiconductor layer comprises a silicon-on-insulator layer with a thickness less than 30 nm.
 16. The method of claim 10 wherein said FET comprises semiconductor S/D regions separated by a semiconducting channel region, said S/D regions and said channel regions comprising different semiconductor materials, said S/D regions being strained, partially strained, or unstrained.
 17. The method of claim 16 wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent.
 18. The method of claim 16 wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiC alloy having a C content equal to or greater than 0.5 atomic percent.
 19. The method of claim 10 performed at a temperature over 150° C. and under 1350° C.
 20. The ion implantation of claim 10 wherein the ion implanted species comprises one or more of As, B, B₁, BF₂, Ge, P, and Sb.
 21. A divided-dose-anneal-in-between (DDAB) method of ion implantation comprising the steps of selecting a substrate including a semiconductor layer; defining first semiconductor layer regions that will be subjected to at least two subsequent ion implantation steps and second semiconductor layer regions that will be protected from said at least two subsequent ion implantation steps; subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a first ion implantation; subjecting said substrate to a first anneal; subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a final ion implantation; and subjecting said substrate to a final anneal; further including the steps of applying a masking layer defining said first and second semiconductor layer regions to the substrate before the first implant step, said masking layer remaining in place until after the final implant step.
 22. The method of claim 21 further including one or more cycles of supplemental implant and annealing steps comprising subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a supplemental ion implantation; and subjecting said substrate to a supplemental anneal; said cycles performed after the first anneal and before the final implant.
 23. An FET device in a semiconductor layer, said FET device comprising source/drain regions subjected to ion implantation while said semiconductor-on-insulator is held at an elevated temperature.
 24. The FET device of claim 23 wherein said elevated temperature is in the range from 70° C. to 900° C.
 25. An FET device in a semiconductor layer, said FET device comprising source/drain regions subjected to a divided-dose-anneal-in-between (DDAB) method of ion implantation comprising the steps of selecting a substrate including a semiconductor layer; defining first semiconductor layer regions that will be subjected to at least two subsequent ion implantation steps and second semiconductor layer regions that will be protected from said at least two subsequent ion implantation steps; subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a first ion implantation; subjecting said substrate to a first anneal; subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a final ion implantation; and subjecting said substrate to a final anneal; wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first anneal.
 26. The FET device of claim 25 wherein said DDAB method of ion implantation further includes one or more cycles of supplemental implant and annealing steps comprising subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a supplemental ion implantation; and subjecting said substrate to a supplemental anneal; said cycles performed after the first anneal and before the final implant, wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first and said supplemental annealing steps.
 27. The FET device of claim 23 wherein said semiconductor layer comprises a bulk semiconductor; a semiconductor-on-insulator layer; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; said semiconductor layer comprising one or more of Si, SiC, Ge, GeC, SiGe, and SiGeC; these materials in layered combinations; these materials strained, partially strained or unstrained.
 28. The FET device of claim 23 wherein said semiconductor layer comprises a silicon-on-insulator layer with a thickness less than 30 nm.
 29. The FET device of claim 23 wherein said FET comprises semiconductor S/D regions separated by a semiconducting channel region, said S/D regions and said channel regions comprising different semiconductor materials, said S/D regions being strained, partially strained, or unstrained.
 30. The FET device of claim 29 wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent.
 31. The FET device of claim 29 wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiC alloy having a C content equal to or greater than 0.5 atomic percent. 